1. Technical Field of the Invention
The present invention relates to an improved input buffer for CMOS integrated circuits.
2. Description of Related Art
Input buffers are a very important subsystem for various blocks on Application Specific Integrated Circuits (ASICs). The input buffers are used as peripheral devices in a block for receiving data from other on-chip devices or external systems. As the operating speed of different blocks in a system varies, the circuitry is also used for buffering the input to the block. Further, the circuitry is used for reducing the parasitic input capacitance of the system as the total input capacitance is reduced to the parasitic input capacitance of the input buffer. Simple input blocks comprise a chain of inverter stages or Schmitt trigger circuitry for input buffering and input capacitance reduction. In order to attain minimum specified noise tolerance, an input low voltage, VIL, and an input high voltage, VIH, switch levels are specified.
With increasing complexity of ASICs, simple buffering and capacitance reduction is not sufficient for modern input circuitry. These systems have to communicate with several other systems working at different voltages. Hence the modern ASIC input buffers must provide protection for the CMOS devices inside the systems during interaction with other local logic blocks or external systems.
At process level, the device dimensions are continuously shrinking to sub-micron technology. Such sub-micron technology devices cannot tolerate high input voltage because of reliability issues due to gate oxide breakdown and punchthrough effect. The gate-oxide breakdown voltage and/or the punchthrough voltage between source and drain are the parameters used to define the maximum input voltage allowed between various nodes of a CMOS device. These devices can operate without experiencing stress due to gate oxide breakdown and punchthrough effects while the input transistor voltages |VGS|, |VDS| and |VGD| do not exceed a prescribed voltage. This has led to the development of low cost and low power integrated circuits requiring lower supply voltages.
With continuous reduction in the CMOS technology sizes and supply voltages, circuit designing for standard protocols is getting more challenging. To meet the standard protocols' electrical specifications, interface circuits using submicron technology devices must work at high input and supply voltages (e.g., 5V, 3.3 V and the like) with high reliability. Interfacing the low-voltage input buffers with high voltage circuitry is a major problem as high input voltage may result in devices experiencing temporary failure or in worst case it may even result in permanent damage to the device. The gate-oxide stress due to high input voltage causes threshold voltage of the device to fluctuate because of tunneling effect and results in reduced device lifetime. To overcome this problem, increasing gate oxide width and using an extended drain scheme can fabricate high voltage tolerant transistors. However, these devices increase the fabrication cost as the process requires extra masks to make device level tuning in the same CMOS baseline process. The fabrication process also results in performance degradation.
Another problem with using low voltage input buffers arises due to increasingly smaller difference between the voltage switch levels (VIL and VIH). An important parameter in these buffers is the toggle voltage, Vtgl, which is defined as the input voltage of an inverter chain, which produces 0.5Vdd at the output for supply voltage Vdd. The toggle voltage Vtgl is used as switching level for the logic in the digital circuits and this value lies between VIH and VIL. The minimum of the difference between Vtgl and VIH and Vtgl and VIL is used to determine the noise margin for the input buffer. For instance, if VIL is at 0.4Vdd and VIH is at 0.6Vdd, Vtgl must lie within the switching window of 0.2Vdd and the maximum noise margin is 0.1Vdd. As a result of reduction in the supply voltage, the switching window is getting progressively smaller resulting in reduced noise margin. This is a cause of concern as the variation in the integrated circuit manufacturing process can introduce a shift in the input switching voltage level Vtgl and result in further reduction in the noise margin for the circuitry.
FIG. 1 is a schematic diagram of a simple 5V tolerant input buffer operating at 3.3V nominal supply voltage. All CMOS devices used in the input buffer are designed in 3.3V CMOS technology. IN is connected to the drain of MOSFET M1, which translates the input signal to a lower voltage at the input node of the buffer for safe operation. When IN receives an input as high as 5V, the input node of the buffer is clamped to (VDDS-VtM1). Because of the substrate bias effect, the threshold voltage Vt of transistor M1 is high (over 1 V) and the buffer input node voltage is comparatively low resulting in safe transistor operation. However if VtM1 is too high, the buffer input node voltage is not sufficiently high resulting in static power consumption as two transistors in the input buffer are in weak inversion or strong sub-threshold mode. Moreover this structure cannot be used for low voltage CMOS devices (i.e. 2.5V) with a high supply voltage (i.e. 3.3V).
FIG. 2 is a schematic diagram of a prior art process compensated input buffer (see, for example, U.S. Pat. No. 6,184,704 to Wang et al.). An improved CMOS input buffer is shown. This improvement reduces the switching level uncertainty range and thus increases the noise margin by compensating for the manufacturing process variations. The invention uses diode connected Px and Nx transistors as resistive compensation devices in the first stage of a multistage digital input buffer. Threshold loss is compensated for by Pt, Nt devices in parallel with Nx, Px respectively. However, as the source of Pt is connected with the gate and drain of device Nx, this circuit does not provide independent control for process variation. Additionally compensation device is not on throughout the transition. Also, this structure cannot be used with low input voltage (i.e., 2.5V) with the input buffer having higher supply voltage (i.e., 3.3V).
Hence, there is need for an input buffer, which is capable of receiving a high input and supply voltage without experiencing degradation of gate oxide lifetime. Further there is need for an input buffer that provides good noise margin with process, temperature and voltage variation. Additionally, there is need for an input buffer that does not need increased process complexity in low voltage CMOS devices for protection against higher input and supply voltages.